1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, it relates to a semiconductor memory device with an improved word line discharging circuit.
2. Description of the Prior Art
FIG. 1 is a schematic diagram showing a conventional word line discharging circuit of a semiconductor memory device having upper and lower word lines. The circuit shown is the word line discharging circuit disclosed in U.S. Pat. No. 4,168,490, with some supplement. The word line driving circuit of FIG. 1 illustrates two row-address lines connected to a row decoder 10 for the purpose of simplification.
Referring to FIG. 1, the output of the row decoder 10 is connected to the upper word line 2 through a word line driving transistor 9 which is connected to the first power supply V.sub.cc. A number of memory cells are connected between the upper word line 2 and the lower word line 3. The power supply V.sub.cc is to provide a prescribed high voltage to the upper and lower word lines 2 and 3 when the row address line thereof is selected. The upper word line 2 and the lower word line 3 are respectively connected to the set input "S" and the reset input "R" of the SR flip flop 4. A series connection of a transistor 5 and a resistor 6 is connected between the lower word line 3 and the second power supply V.sub.EE. The series connection is to discharge the voltage of the lower word line 3 to the power supply V.sub.EE when the row address line is switched from the selected state to the non-selected state. The base of the transistor 5 is connected to the output "Q" of the SR flip flop 4. Another series connection including a transistor 21 and the resistor 22 connected between the lower word line 3 and the power supply V.sub.EE is to allow a constant current flow constantly from the lower word line 3 to the power supply V.sub.EE. Although the description is made for the upper side row address line 50 of FIG. 1, the structure of the lower side row address line 51 is similar to that described in the foregoing, so that the description thereof will be omitted.
FIG. 2 is a schematic diagram of an emitter-coupled bipolar RAM (Random Access Memory) cell, which is one example of the memory cell 1 of the semiconductor memory device shown in FIG. 1. The memory cell comprises two transistors Q1 and Q2 each of which has two emitters, and resistors R1 and R2 respectively connected in series to the transistors Q1 and Q2. The memory cell is connected to the upper word line 2, lower word line 3, complementary bit line 31 and true 1-bit line 32.
In operation, the upper word line 2 and the lower word line 3 are respectively brought to a prescribed high level voltage to carry out the reading or writing operation of the memory cell.
Returning to FIG. 1, the operation of the word line discharging circuit will be described below.
When the row address line thereof is selected, the row decoder 10 applies a high level voltage to the base of the transistor 9, so that the transistor 9 turns on. The upper word line 2 is brought to a prescribed high level voltage by the transistor 9. The lower word line 3 is also brought to a prescribed high level voltage by the voltage applied from the upper word line 2 through the memory cells 1. After reading or writing operation is carried out for a specified memory cell, another row-address line, for example, the lower row-address line of FIG. 1 is selected and the reading or writing operation is carried out in the similar manner. When the reading or writing operation of another row-address line starts, the upper word line 2 and the lower word line 3 of that row-address line which was subjected to the previous reading or writing operation should be brought to their respective standby voltages. Otherwise, the reading or writing operation may possibly be carried out again.
When the upper word line 2 is brought to the high level voltage, the RS flip flop 4 is set and a high level voltage is outputted from the output "Q". The transistor 5 turns on and the lower word line 3 is connected to the power supply V.sub.EE through the transistor 5 and the resistor 6. Thereafter, when another row-address line is selected, the voltages of both word lines 2 and 3 rapidly fall since the transistor 5 has already been conductive. When the voltage of the lower word line 3 is entirely lowered, the RS flip flop is reset and it outputs a low level voltage from the output "Q". The transistor 5 turns off and discharge from the lower word line stops. Therefore, due to the series connection of the transistor 5 and the resistor 6, upper and lower word lines 2 and 3 can be rapidly brought back to the standby voltage after the end of the period in which the row-address line thereof is selected. However, the voltage signal of the lower word line 3 is used for resetting the RS flip flop 4, so that the reset timing changes dependent on the manufacturing diversification of the memory device, the change in the circumferential temperature and the fluctuation in the supply voltage. Consequently, the word lines are not fully discharged or the discharge continues beyond an optimum value. If the discharge time is not sufficient, two or more row address lines are selected causing malfunctions. If the discharge continues, the power consumption increases and the memory device is destroyed due to the high temperature.
FIG. 3 is a timing chart of the word line discharging circuit of FIG. 1, provided for the supplement of the above description.
Referring to FIG. 3, let us assume that the upper row-address line 50 is selected at the time t1 and the lower row-address line 51 is selected at the time t3. In the period between the time t1 and t3, the upper and lower word lines 2 and 3 are respectively brought to the high level voltage. When the upper word line 2 rises to the voltage of a certain value, the RS flip flop 4 is set and the output "Q" is brought to the high level, while it is reset when the lower word line 3 falls to the voltage of a certain value and the output "Q" is brought to the low level. Therefore, the discharge current Io of the lower word line 3 flowing through the transistor 5 and the resistance 6 flows during the period between the time t6 to t4 due to the conduction of the transistor 5. As described above, the RS flip flop 4 turns the transistor 5 on in response to the voltage of the lower word line 3, so that the time t4 is not stable, causing the above described disadvantages. A reference of the prior art of a particular interest to the semiconductor memory device of the present invention is shown in the U.S. Pat. No. 4,366,558 entitled "MEMORY DEVICE WITH FAST WORD-LINE DISCHARGING CIRCUITS" issued to Homma et al. on Dec. 28, 1982. Another reference of the prior art is the U.S. Pat. No. 4,520,462 entitled "SEMICONDUCTOR MEMORY DEVICE" issued to Yamada et al. on May 28, 1985. Both of the above described references disclose a circuit in which the lower word line is rapidly discharged by applying a signal which is delayed from the voltage change of the upper word line.